Carry Ripple Adder
There are many different logic designs to implement a given digital circuit. Speed, cost, power efficiency, and many more, are all aspects that an IC designer needs to look at. Depending on the project requirements, one logic design would be preferable to choose over others. One of the most basic operations in logic is addition. The carry- ripple adder does exactly that. In this project, the CMOS implementation of this circuit is compared to the double-pass transistor implementation of it. HSPICE is used to simulate both circuits. Transient response and power dissipation of both circuits are obtained from the simulations. As expected, DPL circuit is faster than CMOS, but the latter is more power efficient than DPL design. Therefore if only speed of circuit is concerned, we would choose the DPL version. On the other hand if power efficiency is the main concern, CMOS would be a better option.
Key Words: Full Adder, CMOS, DPL, HSpice.
A two-bit carry-ripple adder (CRA) comprises of two full adder connected (cascaded) by one wire. Thus, the two-bit CRA has six inputs and two outputs: the inputs A1, B1, A2 B2, Ci1, & Ci2, as well as the outputs Co1, S1, Co2, & S2. The inputs will vary depending on the logic condition. However for each adder, the combination of two one-bit inputs, are restricted to 4 possibilities. This in turn constrains the actual value of the output. Also, it is important to note that for the CRA the Ci1 is hardwired to ground.
Figure 1: two-bit Carry-Ripple Adder
The two-bit carry ripple adder circuit implemented for this project has many practical uses as the underlying element for more complex digital circuitry. In fact, one must not overlook the most basic operations of the computer; it...